Introduction | Topics | Dates | Organizers | Program Committee | Submission | Program
held in conjunction SC25: The International Conference on High Performance Computing, Networking, Storage and Analysis and in cooperation with IEEE Computer Society
Time/Date: 2:00PM - 5:30PM, Sunday, November 16, 2025
Location: Room TBD, the America’s Center Convention Complex
Introduction
Recent developments of new memory technologies, such as high-bandwidth memory, non-volatile memory, and disaggregated memory, coupled with advanced high-performance interconnects like CXL and NVlink-c2c, further expand the memory hierarchy and increasingly blur the boundary between memory and storage. The growing disparity between computing speed and memory speed, commonly referred to as the Memory Wall problem, remains a critical and enduring challenge in the computing community.
The prevalence of heterogeneous computing, ongoing advancements in the memory hierarchy, and the rise of disaggregated architectures significantly broaden the scope of the challenge of efficiently exploiting memory subsystems on large-scale parallel systems. Simultaneously, the proliferation of large machine learning models, graph processing, quantum computer simulations, and traditional scientific applications facing bottlenecks due to memory latency, bandwidth, and capacity constraints, continue to drive researchers, professionals, and practitioners to enhance memory system design and memory management. Computer architecture, operating systems, storage systems, middleware, performance models, tools, and applications are continuously being optimized or even redesigned to address the performance, programmability, and energy efficiency challenges of Memory Wall. Exploring the intersection of these research areas will enable cohesive and synergistic development and collaboration on the future of memory technologies, systems, middleware, and applications.
This workshop aims to bring together computer science and computational science researchers, from industry, government labs, and academia, concerned with the challenges of efficiently using existing and emerging memory systems. The term performance for memory systems is general, which includes latency, bandwidth, power consumption, and reliability from the aspect of hardware memory technologies to how it is manifested in the application performance.
Topics of Interest
The topics of interest include, but are not limited to:
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Evaluation, characterization, performance analysis, and use cases of emerging memory technologies, including non-volatile memories, high-bandwidth memory, heterogeneous memory, disaggregated memory, etc.
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Software, hardware, and co-design approaches that ease the adoption and optimize the use of processing-in-memory and near-memory computing technologies.
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Programming interfaces or language extensions that improve the programmability of using emerging memory technologies and systems, heterogeneous memory system and multi-dimensional data, and unified memory systems.
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Compiler, runtime, and system techniques for optimizing data layout and placement, page migration, coherence and consistency enforcement, latency hiding and improving bandwidth utilization and energy consumption of heterogeneous memory systems.
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Enhancement or new development for operating systems, storage and file systems, and I/O system that address challenges of existing and emerging memory technologies, heterogeneous memory systems, and the blurred boundary between memory and storage.
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Tools, modeling, evaluation, and case study of memory system behavior and application performance that reveals the limitations and characteristics of existing memory systems.
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Application development and optimization for new memory architecture and technologies and those overcome memory related challenges in their problems.
Important Dates
- Submission Deadline – July 27, 2025 (AoE) – Submission is Open.
- Notifications – September 01, 2025 (AoE)
- Camera Ready Papers – September 29, 2025 (FIRM)
- Workshop – November 16 (Sunday afternoon), 2025
Submission and Review Process
Submission is Open. Login to SC’25 Submission Site, click ‘Make a New Submission’, choose MEMO’25. For SC25, ACM is the SC proceeding publisher. Submissions must use the template at https://www.acm.org/publications/proceedings-template (use \documentclass[sigconf,screen,final]{acmart} in the ACM LaTeX template). Submitted manuscripts may not exceed eight (8) pages in length for regular papers and at least (4) pages for short papers, excluding references.
Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Each paper is expected to receive a minimum of 3 reviews. Double-blind peer-review will be used. Papers will be evaluated based on novelty, technical soundness, clarity of presentation, and impact.
Optionally, authors may submit Artifact Description (AD) or Artifact Evaluation (AE) appendices in the submitted manuscript (see https://sc25.supercomputing.org/program/papers/reproducibility-initiative/).
Program Committee
- Gwendolyn Voskuilen (Sandia National Laboratories, USA)
- Frank Hady (Intel Fellow)
- Kengo Nakajima (The University of Tokyo; RIKEN, Japan)
- Seyong Lee (Oak Ridge National Laboratory, USA)
- Edgar A Leon (Lawrence Livermore National Laboratory, USA)
- Petar Radojkovic (Barcelona Supercomputing Center (BSC); Polytechnic University of Catalonia, Spain)
- Jie Ren College of William & Mary, USA)
- Ivy Peng (KTH Royal Institute of Technology, Sweden)
- Maya Gokhale (Lawrence Livermore National Laboratory, USA)
- Stephen L. Olivier (Sandia National Laboratories, USA)
- Kyle Hale (Illinois Institute of Technology, USA)
Organizers
- Maya Gokhale (Lawrence Livermore National Laboratory, USA)
- Ivy Peng (KTH Royal Institute of Technology, Sweden)
- Kyle Hale (Illinois Institute of Technology, USA)
- Stephen L. Olivier (Sandia National Laboratories, USA)
- Ron Minnich (Hewlett Packard Enterprise, USA)