MEMO'25:

International Workshop on Memory System, Management and Optimization

Nov 16, 2pm-5:30pm, Sunday, St. Louis, USA

Introduction | Topics | Dates | Organizers | Program Committee | Submission | Program

held in conjunction with SC’25 and in cooperation with IEEE Computer Society

2:00PM - 5:30PM, Sunday, November 16, 2025

Room 274, the America’s Center Convention Complex

2:00 - 2:05, MEMO’25 Opening: Maya Gokhale

2:05 - 3:00, Expert Panel: Energy-efficient Memory Technology for maximizing bandwidth and reducing latency

Overview:

Historically, the performance of many HPC applications has been limited by memory bandwidth and latency. Memory bandwidth has increased at an order of magnitude less per year (on average) versus processor performance. Improving memory latency has proven to be even more challenging. This panel brings together industry leaders involved in the NNSA’s Advanced Memory Technology program, which was conceived to address memory performance by inspiring dramatic memory technology advancements for NNSA applications. The panel will discuss future memory technologies, including trends, challenges, and efforts to rethink and overcome memory system performance hurdles.

Moderator:

Panelists:

Josh Fryman (Intel)        Nuwan Jayasena (AMD)        Mike O’Connor (NVIDIA)     Leighton Wilson (Cerebras)

josh        nuwan           mike           Leighton







Josh Fryman is an Intel Fellow and CTO for the Intel Government Technologies group, while also directing the R&D strategy for the public sector. Josh is primarily focused on applied R&D for commercial and government customers for problems that are 3-10 years out on the horizon. Josh has personally been engaged in everything from microprocessor design to system architectures, compilers, runtimes, applications, and algorithms. Josh was chief architect or PI for multiple R&D programs spanning multiple government agencies and technical domains. Josh obtained his BS in Computer Engineering from Univ. of Florida, and his PhD in Computer Architecture from GaTech.

Nuwan Jayasena is a Fellow at AMD Research and Advanced Development with 20+ years’ experience in processor and system design. He leads a team focused on future memory and accelerator architectures. Nuwan holds an M.S and a Ph.D. in Electrical Engineering from Stanford University, is an inventor of over 90 granted US patents, and is an author of over 30 peer-reviewed publications. Prior to AMD, Nuwan was a processor architect at Stream Processors, Inc. and at Nvidia.

Mike O’Connor is a Principal Research Scientist in the Architecture Research Group at NVIDIA, where he develops future DRAM and memory system architectures. In a prior role at NVIDIA, he was the memory system architecture lead for several generations of NVIDIA GPUs. Mike’s career has also included positions at AMD, Texas Instruments, Silicon Access Networks (a network-processor startup), Sun Microsystems, and IBM. At AMD, he drove key aspects of the architecture definition for the initial High-Bandwidth Memory (HBM) specification. Mike has a BSEE from Rice University and an MSEE & PhD from the University of Texas at Austin.

Leighton Wilson is a Senior Member of Technical Staff at Cerebras Systems. He works with customers across industry and government to achieve record-shattering performance on Cerebras’s wafer-scale architecture. He also leads development efforts for the Cerebras SDK for low-level system programming and manages software development for a Cerebras collaboration with the Defense Advanced Research Projects Agency (DARPA). In 2023, he was a Gordon Bell Award finalist for his work with Cerebras and KAUST on scaling the “Memory Wall” for multi-dimensional seismic processing with algebraic compression on Cerebras CS-2 systems. In 2021, Leighton received his PhD in Applied and Interdisciplinary Mathematics and Scientific Computing at the University of Michigan, working with Robert Krasny on fast summation methods for biomolecular electrostatics.

SC Coffee Break (3:00 - 3:30)

Technical Paper Presentations (Moderator: Kyle C. Hale)

CXL focus session (4:50 - 5:30) (Moderator: Stephen Lecler Olivier)

Talk 1: AMAIS — Advanced Memory to Support AI for Science
Talk 2: CXL Shared Memory Case Study: Building a Shared Tier for Lustre Metadata

Closing Remarks (5:30): Maya Gokhale

Introduction

Recent developments of new memory technologies, such as high-bandwidth memory, non-volatile memory, and disaggregated memory, coupled with advanced high-performance interconnects like CXL and NVlink-c2c, further expand the memory hierarchy and increasingly blur the boundary between memory and storage. The growing disparity between computing speed and memory speed, commonly referred to as the Memory Wall problem, remains a critical and enduring challenge in the computing community.

The prevalence of heterogeneous computing, ongoing advancements in the memory hierarchy, and the rise of disaggregated architectures significantly broaden the scope of the challenge of efficiently exploiting memory subsystems on large-scale parallel systems. Simultaneously, the proliferation of large machine learning models, graph processing, quantum computer simulations, and traditional scientific applications facing bottlenecks due to memory latency, bandwidth, and capacity constraints, continue to drive researchers, professionals, and practitioners to enhance memory system design and memory management. Computer architecture, operating systems, storage systems, middleware, performance models, tools, and applications are continuously being optimized or even redesigned to address the performance, programmability, and energy efficiency challenges of Memory Wall. Exploring the intersection of these research areas will enable cohesive and synergistic development and collaboration on the future of memory technologies, systems, middleware, and applications.

This workshop aims to bring together computer science and computational science researchers, from industry, government labs, and academia, concerned with the challenges of efficiently using existing and emerging memory systems. The term performance for memory systems is general, which includes latency, bandwidth, power consumption, and reliability from the aspect of hardware memory technologies to how it is manifested in the application performance.

Topics of Interest

The topics of interest include, but are not limited to:

Important Dates

Submission and Review Process

Submission is Open. Login to SC’25 Submission Site, click ‘Make a New Submission’, choose MEMO’25. For SC25, ACM is the SC proceeding publisher. Submissions must use the template at https://www.acm.org/publications/proceedings-template (use \documentclass[sigconf,screen,final]{acmart} in the ACM LaTeX template). Submitted manuscripts may not exceed eight (8) pages in length for regular papers and at least (4) pages for short papers, excluding references.

Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Each paper is expected to receive a minimum of 3 reviews. Double-blind peer-review will be used. Papers will be evaluated based on novelty, technical soundness, clarity of presentation, and impact.

Optionally, authors may submit Artifact Description (AD) or Artifact Evaluation (AE) appendices in the submitted manuscript (see https://sc25.supercomputing.org/program/papers/reproducibility-initiative/).

Program Committee

Organizers