MEMO'24:

International Workshop on Memory System, Management and Optimization

Nov 17, 2pm-5:30pm, Sunday, Atlanta, USA

Introduction | Topics | Dates | Organizers | Program Committee | Submission | Program

held in conjunction SC24: The International Conference on High Performance Computing, Networking, Storage and Analysis and in cooperation with IEEE Computer Society

Time/Date: 2:00PM - 5:30PM, Sunday, November 17, 2024

Location: Room 302, the Georgia World Congress Center, Atlanta

Program (2:00PM - 5:30PM, Room 302, Sunday, November 17, 2024)

2:00-2:45pm: Invited Talk: Memory & Storage: The Power of HPC/AI

Speaker: Dr. Jongryool Kim (SK Hynix)

Abstract: The growth of AI/Deep learning and data analytics has created many of the most challenging HPC workloads in recent years. Usually HPC/AI applications are driving the need for better memory and storage performance and capacity and despite significant advancements, memory and storage in HPC/AI still encounters several challenges in these. SK hynix has tried to continuous innovation and technological breakthroughs to solve these challenges in Memory/Storage. As part of these efforts, this talk will highlight the key roles that advanced memory and storage play in HPC/AI ecosystem and potential benefits of “Processing Near Data with CXL/HBM/SSD” and “CXL Pooled Memory’s Data Sharing” for HPC/AI Systems.

Bio: Dr. Jongryool Kim is currently serving as the research director of AI System Infra team at SK hynix Inc., located in San Jose, California. He has been conducting research and development of numerous advanced projects such as custom HBM, CXL Pooled memory, computational CXL memory, and object interface storage solution for AI/HPC systems. Additionally, he is a Science Advisory Board (SAB) member of Semiconductor Research Corporation (SRC) JUMP 2.0. Prior to this role, he had served as the cloud system architect at Samsung Mobile division developing and operating a Samsung Cloud data analytics system that manages and analyzes data from all Samsung devices such as smart phones, wearable devices, and home appliances around the world. Additionally, he worked with various R&D teams at Samsung SW R&D Center. He conducted research to improve network and storage IO performance in Cloud.

2:45-3:10pm: PIMnast: Balanced Data Placement for GEMV Acceleration with Processing-In-Memory

Speaker: Mohamed Ibrahim, Mahzabeen Islam, Shaizeen Aga (AMD)

3:10 – 3:30pm, Coffee Break

Speaker: Ellis Giles (Coda Solutions, Adv. Arch. Lab), Peter Varman (Rice University)

3:55-4:20pm: Multi-level Memory-Centric Profiling on ARM Processors with ARM SPE

Speaker: Samuel Miksits, Ruimin Shi (KTH), Maya Gokhale (LLNL), Jacob Wahlgren, Gabin Schieffer, Ivy Peng (KTH)

4:20-4:45pm: Sum Reduction with OpenMP Offload on NVIDIA Grace-Hopper System

Speaker: Zheming Jin (ORNL)

4:45-5:10pm: GMTrans : Combining Scalable Address Translation with Locality Control

Speaker: Yuqing Wang (University of Chicago), Swann Perarnau (Argonne National Laboratory), Andrew Chien (University of Chicago)

5:10-5:35pm: GMTrans : Symmetric Locality: Definition and Initial Results

Speaker: Giordan Escalona, Dylan McKellips, Chen Ding (University of Rochester)

Introduction

Recent developments of new memory technologies, such as high-bandwidth memory, non-volatile memory, and disaggregated memory, coupled with advanced high-performance interconnects like CXL and NVlink-c2c, further expand the memory hierarchy and increasingly blur the boundary between memory and storage. The growing disparity between computing speed and memory speed, commonly referred to as the Memory Wall problem, remains a critical and enduring challenge in the computing community.

The prevalence of heterogeneous computing, ongoing advancements in the memory hierarchy, and the rise of disaggregated architectures significantly broaden the scope of the challenge of efficiently exploiting memory subsystems on large-scale parallel systems. Simultaneously, the proliferation of large machine learning models, graph processing, quantum computer simulations, and traditional scientific applications facing bottlenecks due to memory latency, bandwidth, and capacity constraints, continue to drive researchers, professionals, and practitioners to enhance memory system design and memory management. Computer architecture, operating systems, storage systems, middleware, performance models, tools, and applications are continuously being optimized or even redesigned to address the performance, programmability, and energy efficiency challenges of Memory Wall. Exploring the intersection of these research areas will enable cohesive and synergistic development and collaboration on the future of memory technologies, systems, middleware, and applications.

This workshop aims to bring together computer science and computational science researchers, from industry, government labs, and academia, concerned with the challenges of efficiently using existing and emerging memory systems. The term performance for memory systems is general, which includes latency, bandwidth, power consumption, and reliability from the aspect of hardware memory technologies to how it is manifested in the application performance.

Topics of Interest

The topics of interest include, but are not limited to:

Important Dates

Organizers

Program Committee

Submission and Review Process

Submission is Open. Login to SC’24 submission site, click ‘Make a New Submission’, choose MEMO’24. For SC24, IEEE is the SC proceeding publisher. Submissions must use the template of IEEE conference proceedings: two-column, US letter. The minimum number of pages is 5 pages, including references, and there is no upper limit of pages. IEEE will be providing a unique copyright submission site, and access to PDF eXpress to validate final pdfs. Additional guidelines, including the copyright notice for the camera-ready, will be provided at a later time. Camera ready papers are required to be formatted the same as the main conference papers. Each paper is expected to receive a minimum of 3 reviews. Double-blind peer-review will be used. Papers will be evaluated based on novelty, technical soundness, clarity of presentation, and impact. The Technical Program Committee reserves the right to reject incorrectly formatted papers.